Designing Counters with VHDL


This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Designing Counters with VHDL”.

1. The ring counter is a serial shift register with feedback from the output of the last flip-flop to the input of the first flip-flop.
a) True
b) False

2. Which of the following flip-flop is used by the ring counter?
a) D flip-flops
b) SR flip-flops
c) JK flip-flops
d) T flip-flops

3. ‘shift_reg’ is used to initialize the _____________ in the shift register.
a) LSB
b) MSB
c) Register type
d) Register bits

4. How many types of shift operators are there in VHDL?
a) Three
b) Four
c) Five
d) Six

5. How many types of the data type are there in the ring counter?
a) One
b) Two
c) Three
d) More than three

6. In __________ counter universal clock is not used.
a) Synchronous counter
b) Asynchronous counter
c) Decade counter
d) Ring counter

7. Synchronous counter use ________ global clock, unlike asynchronous counter.
a) One
b) Two
c) Three
d) zero

8. Asynchronous counters are generally used in circuits with higher frequency, where a large number of bits are involved.
a) True
b) False

9. How many different states does a decade counter count?
a) Eight
b) Nine
c) Ten
d) Eleven

10. The number of flip-flops used in a counter is _________ number of states in the counter.
a) Greater than
b) Less than
c) Equal to
d) Greater than equal to

11. Two decade counters cascaded together will divide the input frequency by ________
a) 10
b) 100
c) 1000
d) 10000

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