Flattening and Factoring of Functions MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Flattening and Factoring of Functions”.

1. Flattening creates a flat signal representation of ______ levels.
a) 1
b) 2
c) 3
d) 4

2. How will you flatten the following function?

a = b AND c;
b = x OR (y AND z);
c = q OR w;

a) a = (x AND q) OR (q AND y AND z) OR (w AND x) OR (w AND y AND z);
b) a = (x OR q) AND (q OR y OR z) AND (w OR x) AND (w OR y OR z);
c) a = (x AND b) OR (c AND y AND z) OR (c AND x) OR (b AND y AND z);
d) a = (w AND q) OR (w AND y AND z) OR (q AND x) OR (q AND y AND z);

3. What is the process of flattening?
a) Converting an optimized function to unoptimized form
b) Converting a Boolean function to PAL format
c) Converting a Boolean function to PLA format
d) Converting a Boolean function to POS form

4. What is the result of flattening of functions?
a) Increased readability
b) Increased speed
c) Decreased speed
d) Decreased readability

5. Which of the following is the opposite of flattening of functions?
a) Structure
b) Adding intermediate nodes
c) Un-flattening
d) Factoring

6. In which of the following functions, the flattening is difficult?
a) Functions containing many XOR
b) Functions which are already minimal
c) Functions which are slow due to intermediate nodes
d) Functions which is always false

7. The main advantage of using factoring is ________
a) Reducing the speed
b) Reducing the number of terms
c) Adding intermediate nodes
d) Reducing flattening

8. Which factor can be there in the following two functions?

x = a AND b OR a AND c;
y = b OR c OR d

a) a AND b
b) b OR a
c) b AND c
d) b OR c

9. What is another name for the factoring of functions?
a) De-flattening
b) Intermediation
c) Structuring
d) De-structuring

10. What would be the ideal case for a design?
a) Using factoring only
b) Using flattening only
c) Using both flattening and factoring
d) Neither using flattening and nor factoring

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