Signal Assignment – 1 MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Signal Assignment – 1″.

1. How can we use an assignment statement as a sequential assignment?
a) By using keyword WAIT
b) By using a delay mechanism
c) By using conditional statements
d) By using it in any process

2. The sequential assignment statement is activated, whenever ________
a) The waveform associated changes its value
b) The process is terminated
c) The execution is scheduled
d) The value of the target is needed

3. The signal assignment is considered as a ________
a) Concurrent statement
b) Sequential statement
c) Subprogram
d) Package declaration statement

4. The concurrent assignment statement is activated whenever ______
a) The execution is scheduled
b) The value of the target is needed
c) The waveform associated changes its value
d) The process is terminated

5. The conditional assignment statement is a _________ assignment.
a) Sequential
b) Concurrent
c) Selected
d) None of the above

6. Which of the following is correct syntax for a signal assignment statement (if {} specifies an optional part)?
a) target <= {delay_mechanism} waveform;
b) target <= delay_mechanism waveform;
c) target <= delay_mechanism {waveform};
d) target <= {delay_mechanism} {waveform} value;

7. Sequential assignments are synthesizable.
a) True
b) False

8. Which of the following can’t be a mode for target operand of assignment statement?
c) OUT
d) IN

9. Delays are generally ignored in ________ assignments statements.
a) Concurrent
b) Conditional
c) Sequential
d) Selected

10. Which of the following is a keyword used for conditional assignment?
a) IF
c) FOR
d) END

11. Which of the following is a variable assignment statement?
a) <=
b) :=
c) =>
d) ==

12. For a signal used in sequential assignment, it can have _______ driver(s).
a) 1
b) 2
c) 3
d) 4

Leave a Reply

Your email address will not be published. Required fields are marked *