Aliases and Qualified Expressions

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Aliases and Qualified Expressions”.

1. What does an alias declaration actually do?
a) Creates a new object
b) Doesn’t create a new object
c) Creates a new signal
d) Overwrites a file

2. Which of the following is the correct syntax for declaring an alias?
a) ALIAS alias_name : object_name;
b) ALIAS alias_name ; object_name;
c) ALIAS alias_name – alias_type object_name;
d) ALIAS alias_name : alias_type object_name;

3. For what purpose in the following, one can use alias?
a) To divide the complex part into smaller slices
b) To decrease the simulation time
c) To make use of same memory
d) To assign different memory locations

4. Which of the following can’t be aliased?
a) Signal
b) Loop variable
c) Variable
d) File

5. An alias of array type can reverse the order of the array.
a) True
b) False

6. In what way the qualified expression differs from a normal expression?
a) It has a keyword qualified in front of it
b) Its type is explicitly defined
c) Its range is defined
d) It is similar to simple expression but is synthesizable

7. Which of the following is the correct syntax to define a qualified expression?
a) (expression)’ type
b) (expression)” type
c) type’ (expression)
d) type” (expression)

8. Where one should use the qualified expression?
a) In all overloaded functions
b) In overloaded functions with different number of parameters
c) In overloaded functions with different parameter names
d) In overloaded functions with different parameter types

9. Which one of the following would be the best use of qualified expression?
a) Function overloaded with bit and integer types
b) Function overloaded with bit_vector and std_logic_vector
c) Function overloaded with bit_vector and std_logic
d) Function overloaded with std_logic_vector and bit

10. A qualified expression is synthesizable in VHDL.
a) True
b) False

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