Asynchronous Preset and Clear

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Asynchronous Preset and Clear”.

1. What type of inputs is preset and clear?
a) Data input
b) Output
c) Clock input
d) Control input

2. Clear (CLR) or preset (PRE) with a bar above them shows that they have ________
a) Active high input
b) Active low input
c) Clocked input
d) No input

3. Asynchronous inputs are also called override inputs.
a) True
b) False

4. The output of the flip-flop _______ when both the input, preset and clear are active low at the same time.
a) Is set to 1
b) Is set to 0
c) Becomes X (Don’t care)
d) Is controlled by clock

5. What is the state of PRESET input?
a) Reset
b) Set
c) Invalid
d) Don’t care

6. What is the state of CLEAR input?
a) Reset
b) Set
c) Invalid
d) Don’t care

7. What happens if both the inputs PRE and CLR are activated?
a) Flip-flop is reset
b) Flip-flop is set
c) Invalid State
d) No output

8. Which of the following input on a flip-flop has control over the outputs?
a) Data input
b) Clock
c) Enable
d) Preset

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