Configurations MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Configurations”.

1. It is necessary to use configuration to bind entity to the architecture in case of structural modeling.
a) True
b) False

2. Among the following cases, when the configurations must be used?
a) One entity and two architectures
b) Two entities and one architecture
c) Two entities and no architecture
d) One entity and no architecture

3. Configuration is generally associated with ________
a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) All of the modeling styles

4. Which of the following is correct syntax for defining a configuration?
a)

    FOR instantation_label : component_name
    USE ENTITY library_name.entity_name[(architecture_name)];

b)

    FOR instantation_label : component_name
    USE ENTITY entity_name[(architecture_name)];

c)

    FOR component_name : instantiation_label
    USE ENTITY library_name.entity_name[(architecture_name)];

d)

    FOR component_name : instantiation_label
    USE ENTITY entity_name[(architecture_name)];

5. What is the use of default configurations?
a) To bind the architecture and entity
b) To configure block statements in architecture
c) To bind generics with architecture
d) To bind components with entity

6. Which of the following part is optional in a configuration statement?
a) Instantiation label
b) Library name
c) Entity name
d) Architecture name

7. Which of the following is true about configurations?
a) To use architecture in configurations, it must be first added to some library
b) A configuration can use more than one architecture for an entity
c) To use an entity in configurations, it must be first added to some library
d) A configuration can’t use any architecture for any entity

8. It is necessary to define entity and configuration in the same library.
a) True
b) False

9. Apart from the components ________ can also be associated with configurations.
a) Constants
b) Generics
c) Integers
d) Signals

10. As a VHDL designer, what should you make sure about the design so that it is synthesized correctly?
a) It must use a configuration when more than one architecture is used
b) All the component ports and entity ports must be matched
c) A configuration must be there always
d) A configuration is used when ports are mismatched

11. Which of the following is not a part of the configuration statement?
a) Architecture specification
b) Instance specification
c) Binding indication
d) Library binding

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