Designing Mealy Type FSM with VHDL

VHDL

This set of VHDL Puzzles focuses on “Designing Mealy Type FSM with VHDL”.

1. Output values of mealy type FSM are determined by its ________
a) Input values
b) Output values
c) Both input values and current state
d) Current state

2. What kind of output does mealy machine produce?
a) Asynchronous
b) Synchronous
c) Level
d) Pulsed

3. States in FSM are represented by ________
a) Bits
b) Bytes
c) Word
d) Character

4. What is the first step in writing the VHDL for an FSM?
a) To define the VHDL entity
b) Naming the entity
c) Defining the data type
d) Creating the states

5. A Mealy machine is safer to use.
a) True
b) False

6. Which of the following react faster to inputs?
a) Sequencer
b) Generators
c) Mealy machines
d) Moore machines

7. What is the first state of FSM?
a) Wait loop state
b) Initial state
c) Output state
d) Activate pulse state

8. Mealy machines have _________ states than Moore machine.
a) Fewer
b) More
c) Equal
d) Negligible

9. Mealy type FSM has a memory element.
a) True
b) False

10. In mealy type FSM, the path is labelled by which of the following?
a) Inputs
b) Outputs
c) Both inputs and outputs
d) Current state

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