Designing Moore Type FSM with VHDL MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Designing Moore Type FSM with VHDL”.

1. Moore machine output is synchronous.
a) True
b) False

2. State transition happens _______ in every clock cycle.
a) Once
b) Twice
c) Thrice
d) Four times

3. Finite state machines are combinational logic systems.
a) True
b) False

4. What happens if the input is low in FSM?
a) Change of state
b) No transition in state
c) Remains in a single state
d) Invalid state

5. Output values of Moore type FSM are determined by its ________
a) Input values
b) Output values
c) Clock input
d) Current state

6. What happens if the input is high in FSM?
a) Change of state
b) No transition in state
c) Remains in a single state
d) Invalid state

7. In FSM diagram what does circle represent?
a) Change of state
b) State
c) Output value
d) Initial state

8. In the FSM diagram, what does the information below the line in the circle represent?
a) Change of state
b) State
c) Output value
d) Initial state

9. In the FSM diagram, what does arrow between the circles represent?
a) Change of state
b) State
c) Output value
d) Initial state

10. Moore machine has _________ states than a mealy machine.
a) Fewer
b) More
c) Equal
d) Negligible

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