EDA Tools

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “EDA Tools”.

1. What is the full form of VHDL?
a) Verilog Hardware Description Language
b) Very High speed Description Language
c) Variable Hardware Description Language
d) Very high speed Hardware Description Language

2. What is the basic use of EDA tools?
a) Communication of Electronic devices
b) Fabrication of Electronics hardware
c) Electronic circuits simulation and synthesis
d) Industrial automation

3. After compiling VHDL code with any EDA tool, we get __________
a) Final device
b) FPGA
c) Optimized netlist
d) Netlist

4. Which of the following is not an EDA tool?
a) Visual C++
b) Quartus II
c) Xilinx ISE
d) MaxPlus II

5. The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________
a) Simulation
b) Synthesis
c) Optimization
d) Verification

6. Place and Route EDA tools are used to take the design netlist and implement the design in the device.
a) True
b) False

7. An Antifuse programming technology is associated with _________
a) CPLDs
b) FPGAs
c) SPLDs
d) ASICs

8. Which of the following is not a back end EDA tool?
a) Floor planning tools
b) Placement tools
c) Routing tools
d) Simulators

9. What are the differences between simulation tools and synthesis tool?
a) Simulators are used to check the performance of circuit and Synthesis tools are for the fabrication of circuits
b) Simulators and Synthesis tools works exactly same
c) Simulators are used just to check basic functionality of the circuit and Synthesis tools includes timing constraints and other factors along with simulation
d) Simulation finds the error in the code and Synthesis tool corrects the code

10. What is the extension of the netlist file; input to the place and route EDA tools?
a) EIDF
b) SDF
c) TXT
d) CPP

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