Generate Statement MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Generate Statement”.

1. There are _______ types of GENERATE statement in VHDL.
a) 2
b) 3
c) 4
d) 5

2. A generate statement is generally associated with ________ modeling.
a) Behavioral
b) Data flow
c) Structural
d) Behavioral and data flow

3. Generate statement is a _______ statement.
a) Concurrent
b) Sequential
c) Concurrent as well as sequential
d) Process

4. What is the correct syntax for FOR generate statement?
a)

label : FOR parameter IN range GENERATE
      begin
      declarations;
      concurrent statement
      END GENERATE label;

b)

label : FOR parameter IN range GENERATE
      declarations;
      begin
      concurrent statement
      END GENERATE label;

label : FOR parameter IN range GENERATE
      declarations;
      begin
      sequential statement
      END GENERATE label;

d)

label : FOR parameter IN range GENERATE
      declarations;
      begin
      sequential statement
      END label GENERATE;

5. Which of the following is a correct statement for IF generate statement?
a)

     IF condition GENERATE
     begin
     declarations;
     concurrent_statements;
     END GENERATE label;

b)

     label : IF condition GENERATE
     declarations;
     begin
     sequential_statements;
     END GENERATE label;

c)

     IF condition GENERATE
     declarations;
     begin
     sequential_stataements;
     END GENERATE label;

d)

     label : IF condition GENERATE
     declarations;
     begin
     concurrent_statements;
     END GENERATE label;

6. Using a label is compulsory with a GENERATE statement.
a) True
b) False

7. FOR generate creates ____________ objects.
a) Dissimilar
b) Unique
c) Different
d) Similar

8. Generate statements can’t be nested.
a) True
b) False

9. What is realized in the code given below?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_logic IS
GENERIC n : INTEGER := 8;
PORT (sig1 : bit_vector(n-1 DOWNTO 0);
             Sig2 : bit_vector(n-1 DOWNTO 0));
END my_logic;
ARCHITECTURE test OF my_logic IS
COMPONENT or2
   PORT(a0, a1 : IN BIT;
                z         : OUT BIT);
END COMPONENT or
BEGIN
ORARRAY : FOR i IN (n-1) DOWNTO 0 GENERATE
                   or_gate : or2
PORT MAP ( a0 => sig1(i),
                       A1 => sig2(i),
                         z => y(i));
END GENERATE ORARRAY;
END test;

a) 7- Bit parallel adder ignoring the carry
b) 7- Bit parallel adder including the carry
c) 8- Bit parallel adder ignoring the carry
d) 8- bit parallel adder including the carry

10. Which of the following is legal?
a)

     label : FOR n IN 7 DOWNTO 0 GENERATE
     concurrent_statement;
      END GENERATE;

b)

     label : FOR n IN 7 DOWNTO 0 GENERATE
     declarations;
      concurrent_statement;
      END GENERATE;

c)

    label : FOR n IN 7 DOWNTO 0 GENERATE
     begin
     declarations;
     concurrent_statement;
      END GENERATE;

d)

    label : FOR n IN 7 DOWNTO 0 GENERATE
    begin
    concurrent_statement;
     END GENERATE label

11. Which of the following is not possible to use inside the FOR generate statement?
a) IF
b) IN
c) EXIT
d) PORT MAP

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