Generics

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Generics”.

1. In which part of the VHDL code, generics are declared?
a) Package declaration
b) Entity
c) Architecture
d) Configurations

2. Which of the following is correct declaration for a generic?
a) GENERIC (name : type := initial_value);
b) GENERIC (type : name := initial_value);
c) GENERIC (name : type <= initial_value);
d) GENERIC ( ype : name <= initial_value);

3. What is the main use of the generic parameter?
a) Defining constant type
b) Assigning some initial value to constant
c) Reusability
d) Using constant type within the entity

4. More than one generic parameter can be defined in a single entity.
a) True
b) False

5. Which of the following is true about Generics?
a) Generics can be assigned information as part of simulation run
b) Generics cannot be assigned information as part of simulation run
c) Generic passes data to an entity which is not instance specific
d) Results of simulation can modify the value of generics

6. A generic can’t be declared in a component declaration.
a) True
b) False

7. In most synthesis tools, only generics of type ________ are supported.
a) INTEGER
b) REAL
c) BIT_VECTOR
d) STD_LOGIC

8. GENERIC (n : INTEGER := 8); In this statement, the mode of generic ‘n’ is _______
a) Integer
b) Real
c) Generic
d) No Mode

9. Which function is used to map a generic on design?
a) Port map()
b) Generic()
c) Generic map()
d) Port

10. Generics in VHDL can be treated as _______
a) Global variable
b) Local variable
c) Variable
d) Signal

11. Which of the following can be used as a generic in a complex digital design with many inputs and two outputs?
a) Number of outputs
b) Number of inputs
c) Intermediate signals
d) No parameter

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