Implementing Combinational Circuits with VHDL

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Implementing Combinational Circuits with VHDL”.

1. Which of the following is a not a characteristics of combinational circuits?
a) The output of combinational circuit depends on present input
b) There is no use of clock signal in combinational circuits
c) The output of combinational circuit depends on previous output
d) There is no storage element in combinational circuit
red

2. Sequential code can’t be used to design combinational circuit.
a) True
b) False

3. Which of the following is not a combinational circuit?
a) Adder
b) Code convertor
c) Multiplexer
d) Counter

4. The code given below is a VHDL implementation of _________

ARCHITECTURE my_circuit OF my_logic IS
BEGIN
WITH ab SELECT
y <= x0 WHEN “00”;
         x1 WHEN “01”;
         x2 WHEN “10”;
         x3 WHEN “11”;
END my_circuit;

a) 4 to 1 MUX
b) 1 to 4 DEMUX
c) 8 to 1 MUX
d) 1 to 8 DEMUX

5. Which of the following line of the code contains an error?

L1: ARCHITECTURE mux1 OF mux IS
L2: BEGIN
L3: y<= x0 WHEN x = ‘0’ ELSE
L4:   <= x1 WHEN x = ‘1’;
L5: END mux1;

a) L2
b) L3
c) L4
d) No error

6. In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to implement the same?
a) WITH-SELECT
b) WITH-SELECT-WHEN
c) IF-ELSE
d) CASE

7. Which of the following entity declares the ports of a 3 by 8 decoder?
a)

    ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
     END decoder;

b)

     ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
     END decoder;

c)

     ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
     END decoder;

d)

     ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
     END decoder;

8. For using a process to implement a combinational circuit, which signals should be in the sensitivity list?
a) Inputs of the circuit
b) Outputs of the circuit
c) Both of the Inputs and Outputs
d) No signal should be in the sensitivity list

9. A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively?
a) Binary, Octal
b) Octal, Binary
c) Hexadecimal, Binary
d) Binary, Hexadecimal

10. Following entity may represent a ________ circuit.

ENTITY my_circuit IS
PORT (a, b : IN STD_LOGIV_VECTOR(3 DOWNTO 0);
              x    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
              y    : OUT STD_LOGIC);
END my_circuit;

a) Half adder
b) Full adder
c) Multiplexer
d) Parallel adder

11. The process statement used in combinational circuits is called ______ process.
a) Combinational
b) Clocked
c) Unclocked
d) Sequential

12. Why we need to include all the input signals in the sensitivity list of the process?
a) To monitor the output continuously
b) To monitor the input continuously
c) To make the circuit synthesizable by EDA tools
d) No special purpose

13. If only two bit vectors are allowed to use in the VHDL code, then how many number of MUX will be required to implement 4 to 1 MUX?
a) 1
b) 2
c) 3
d) 4

14. A package is designed called mux4to1_package, in which a component called mux4to1 is defined, which is a 4 to 1 multiplexer. Now a user wants to design a 16 to 1 MUX by using the same component only, how many times he needs to use the PORT MAP statement?
a) 2
b) 3
c) 4
d) 5

15. In designing a 2 to 1 demultiplexer with input d, output y and select line s, which of the following is a correct process statement?
a) PROCESS(d)
b) PROCESS(d(0), d(1), s)
c) PROCESS(d(0), d(1))
d) PROCESS(d, s, y)

16. The given code represents a convertor. Which kind of convertor it is?

ENTITY convert IS
PORT(b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           x : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END convert;
ARCHITECTURE convertor OF covert IS
BEGIN
PROCESS(b)
BEGIN
CASE b IS
WHEN “0000” => x <= “1111110”;
WHEN “0001” => x <= “0110000”;
WHEN “0010” => x <= “1101101”;
WHEN “0011” => x <= “1111001”;
WHEN “0100” => x <= “0110011”;
WHEN “0101” => x <= “1011011”;
WHEN “0110” => x <= “1011111”;
WHEN “0111” => x <= “1110000”;
WHEN “1000” => x <= “1111111”;
WHEN “1001” => x <= “1110011”;
WHEN OTHERS => x <= “0000000”;
END CASE;
END PROCESS;
END convertor;

a) Gray to BCD
b) 7 segment to BCD
c) BCD to gray
d) BCD to 7 segment display

17. What is the function of the below code?

ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
             Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;

a) To count number of ones in the given data
b) To count number of zeroes in the given data
c) To reverse the order of given data
d) To perform binary multiplication of two data inputs
.

18. What will be the value of count output, if the data din is 11001111?

ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
             Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;

a) 6
b) 0110
c) 2
d) 0010

19. In the combinational process, the use of output signal in the sensitivity list is illegal.
a) True
b) False

20. A parity generator is a combinational circuit and is designed by using a combinational process.
a) True
b) False

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