Implementing Gates with Different Modelling – 1 MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Implementing Gates with Different Modelling – 1″.

1. Which of the following gate is a universal gate?
a) AND
b) NAND
c) EXOR
d) EXNOR

2. By how many modeling styles, the gates in VHDL can be implemented?
a) 1
b) 2
c) 3
d) 4

3. Which of the following is a basic building block of digital logic?
a) Wires
b) Nets
c) Gates
d) Flip-flops

4. Which of the following is not needed when modeling a simple gate?
a) Library
b) Entity
c) Architecture
d) Configuration

5. What is the type of modeling used in the code given below?

ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= ‘1’ WHEN a =’1’ AND b = ‘0’;
       ‘0’ WHEN OTHERS;
END my_arch;

a) Behavioral
b) Dataflow
c) Structural
d) Combinational

6. Which kind of modeling is used in the following description?

ARCHITECTURE my_arch OF my_design IS
BEGIN
c<= a OR b;
END my_arch;

a) Behavioral
b) Data flow
c) Structural
d) Behavioral and Dataflow

7. The architecture describes _______ gate implemented by _________ modeling.

ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= NOT(a OR b);
END my_arch;

a) Or, behavioral
b) Not, Dataflow
c) Nor, behavioral
d) Nor, Dataflow

8. Which of the logic gate is described by the following model?

ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT my_comp IS
PORT( a, b : IN std_logic;
             y     : OUT std_logic);
END COMPONENT;
L1 : my_comp PORTMAP( x, y, z);
END my_arch;

a) OR
b) NOT
c) AND
d) Can’t be determined

9. Which logic gate is described by the following model, also specify the type of modeling used?

ARCHITECTURE my_arch OF my_design IS
BEGIN
WITH ab SELECT
y <= 0 WHEN “11”
        1 WHEN OTHERS
END my_arch;

a) NAND, Behavioral
b) NOR, Behavioral
c) NAND, Dataflow
d) NOR, Dataflow

10. The design below can’t be of ________ gate.

ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT or_comp IS
PORT( a, b : IN std_logic;
             y     : OUT std_logic);
END COMPONENT;
L1 : or_comp PORTMAP( x, y, z);
END my_arch;

a) AND
b) OR
c) NOT
d) NAND

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