Implementing Gates with Different Modelling – 2 MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Implementing Gates with Different Modelling – 2″.

1. Which of the following logic describes the EXOR gate?
a) y <= ((not a) OR (not b)) AND ((not a) OR (not b));
b) y <= ((not a) OR b) AND (a OR (not b))
c) y <= ((not a) AND (not b)) OR ((not a) AND (not b));
d) y <= ((not a) AND b) OR (a AND (not b));

2. What logic circuit is described by the following code?

ARCHITECTURE gate OF my_gate IS
BEGIN
WITH ab SELECT
y<= 0 WHEN “01” OR “10”;
        1 WHEN OTHERS;
END gate;

a) NAND
b) NOR
c) EXOR
d) EXNOR

3. What is the minimum number of NAND gates required to implement an EXOR gate?
a) 2
b) 3
c) 4
d) 5

4. Sometimes gates modeled with ________ modeling may behave differently.
a) Dataflow
b) Behavioral
c) Structural
d) Structural and Behavioral

5. Which of the following option represents a structural model for not gate?
a)

    Architecture not_gate OF my_func IS
    BEGIN
    x: IN STD_LOGIC;
    y: OUT STD_LOGIC;
    END not_gate;

b)

    Architecture not_gate OF my_func IS
    BEGIN
    x: IN STD_LOGIC;
    y: OUT STD_LOGIC;
    y<= NOT x;
    END not_gate;

c)

   Architecture not_gate OF my_func IS
    BEGIN
   COMPONENT NOT IS
   Port(  x: IN STD_LOGIC;
   y: OUT STD_LOGIC);
   END COMPONENT;
    END not_gate;

d)

   Architecture not_gate OF my_func IS
    BEGIN
    COMPONENT not1 IS
    PORT( x: IN STD_LOGIC;
    y: OUT STD_LOGIC);
    END COMPONENT;
    END not_gate;

6. The odd behavior of gates in dataflow modeling may be the result of ________
a) Sequential statements
b) Wrong logic definitions
c) Concurrency
d) Inappropriate assignments

7. In CPLD, there are many input switches arranged in a switch bank, if an AND gate is behaving oddly but could be the reason?
a) Incorrect interconnections
b) Concurrent execution of statements
c) Mismatch of ports name and switches
d) Wrong libraries included

8. Generally, structural modeling is used with another modeling style.
a) True
b) False

9. For gates, which of the following modeling style will corresponds to shortest code?
a) Behavioral
b) Data flow
c) Structural
d) Both data flow and behavioral

10. Which of the following doesn’t corresponds to NAND gate?
a)

y <= NOT( a AND b)

b)

y <= NOT a OR NOT b

c)

y <= NOT a AND NOT b

d)

   WITH ab SELECT
    y <= 0 WHEN ”11”
    1 WHEN OTHERS

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