This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Implementing Gates with Different Modelling”.
1. Which of the following is a basic building block of digital logic?
a) Wires
b) Nets
c) Gates
d) Flip-flops
2. Which of the following gate is a universal gate?
a) AND
b) NAND
c) EXOR
d) EXNOR
3. By how many modeling styles, the gates in VHDL can be implemented?
a) 1
b) 2
c) 3
d) 4
4. Which of the following is not needed when modeling a simple gate?
a) Library
b) Entity
c) Architecture
d) Configuration
5. Which kind of modeling is used in the following description?
ARCHITECTURE my_arch OF my_design IS BEGIN c<= a OR b; END my_arch;
a) Behavioral
b) Data flow
c) Structural
d) Behavioral and Dataflow
6. What is the type of modeling used in the code given below?
ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= ‘1’ WHEN a =’1’ AND b = ‘0’;
‘0’ WHEN OTHERS;
END my_arch;
a) Behavioral
b) Dataflow
c) Structural
d) Combinational
7. The architecture describes _______ gate implemented by _________ modeling.
ARCHITECTURE my_arch OF my_design IS BEGIN y <= NOT(a OR b); END my_arch;
a) Or, behavioral
b) Not, Dataflow
c) Nor, behavioral
d) Nor, Dataflow
8. Which logic gate is described by the following model, also specify the type of modeling used?
ARCHITECTURE my_arch OF my_design IS
BEGIN
WITH ab SELECT
y <= 0 WHEN “11”
1 WHEN OTHERS
END my_arch;
a) NAND, Behavioral
b) NOR, Behavioral
c) NAND, Dataflow
d) NOR, Dataflow
9. Which of the logic gate is described by the following model?
ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT my_comp IS
PORT( a, b : IN std_logic;
y : OUT std_logic);
END COMPONENT;
L1 : my_comp PORTMAP( x, y, z);
END my_arch;
a) OR
b) NOT
c) AND
d) Can’t be determined
.
10. The design below can’t be of ________ gate.
ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT or_comp IS
PORT( a, b : IN std_logic;
y : OUT std_logic);
END COMPONENT;
L1 : or_comp PORTMAP( x, y, z);
END my_arch;
a) AND
b) OR
c) NOT
d) NAND
11. What is the minimum number of NAND gates required to implement an EXOR gate?
a) 2
b) 3
c) 4
d) 5
12. Which of the following logic describes the EXOR gate?
a) y <= ((not a) OR (not b)) AND ((not a) OR (not b));
b) y <= ((not a) OR b) AND (a OR (not b))
c) y <= ((not a) AND (not b)) OR ((not a) AND (not b));
d) y <= ((not a) AND b) OR (a AND (not b));
13. What logic circuit is described by the following code?
ARCHITECTURE gate OF my_gate IS
BEGIN
WITH ab SELECT
y<= 0 WHEN “01” OR “10”;
1 WHEN OTHERS;
END gate;
a) NAND
b) NOR
c) EXOR
d) EXNOR
14. Sometimes gates modeled with ________ modeling may behave differently.
a) Dataflow
b) Behavioral
c) Structural
d) Structural and Behavioral
15. The odd behavior of gates in dataflow modeling may be the result of ________
a) Sequential statements
b) Wrong logic definitions
c) Concurrency
d) Inappropriate assignments
16. Which of the following option represents a structural model for not gate?
a)
Architecture not_gate OF my_func IS
BEGIN
x: IN STD_LOGIC;
y: OUT STD_LOGIC;
END not_gate;
b)
Architecture not_gate OF my_func IS
BEGIN
x: IN STD_LOGIC;
y: OUT STD_LOGIC;
y<= NOT x;
END not_gate;
c)
Architecture not_gate OF my_func IS
BEGIN
COMPONENT NOT IS
Port( x: IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
END not_gate;
d)
Architecture not_gate OF my_func IS
BEGIN
COMPONENT not1 IS
PORT( x: IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
END not_gate;
.
17. In CPLD, there are many input switches arranged in a switch bank, if an AND gate is behaving oddly but could be the reason?
a) Incorrect interconnections
b) Concurrent execution of statements
c) Mismatch of ports name and switches
d) Wrong libraries included
18. For gates, which of the following modeling style will corresponds to shortest code?
a) Behavioral
b) Data flow
c) Structural
d) Both data flow and behavioral
19. Generally, structural modeling is used with another modeling style.
a) True
b) False
20. Which of the following doesn’t corresponds to NAND gate?
a)
y <= NOT( a AND b)
b)
y <= NOT a OR NOT b
c)
y <= NOT a AND NOT b
d)
WITH ab SELECT
y <= 0 WHEN ”11”
1 WHEN OTHERS