LOOP Statement

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “LOOP Statement ”.

1. A loop statement is used where we needs to ________
a) Select one from many choices
b) Check a condition
c) Repeat the statements
d) Choose one from two cases

2. Loop is a ________ statement.
a) Concurrent
b) Sequential
c) Assignment
d) Functional

3. How many styles of loop statement does the VHDL have?
a) 2
b) 3
c) 4
d) 5

4. What is the use of FOR loop?
a) To repeat the statement finite number of times
b) To repeat the statement until any condition holds true
c) To repeat the statements for infinite time
d) To repeat statements inside until any condition is false

5. Which of the following is correct syntax for defining FOR LOOP?
a)

    label : FOR LOOP loop_specification
     sequential_statements;
     ….
     END LOOP label;

b)

    label : FOR loop_specification LOOP
     sequential_statements;
     ….
     END FOR LOOP;

c)

    label : FOR LOOP loop_specification
     sequential_statements;
     ….
     END FOR LOOP;

d)

    label : FOR loop_specification LOOP
     sequential_statements;
     ….
     END LOOP label;

6. What is the use of WHILE loop?
a) To repeat the statement finite number of times
b) To repeat the statement until any condition holds true
c) To repeat the statements for infinite time
d) To repeat statements inside until any condition is false

7. Which of the following is correct syntax for WHILE LOOP?
a)

   label: WHILE LOOP specification IS
    sequential_statements;
    END LOOP;

b)

    label: WHILE LOOP condition
    sequential_statements;
    END LOOP label;

c)

    label: WHILE condition LOOP
    sequential_statements;
    END LOOP label;

d)

   label: WHILE specification LOOP
    sequential_statements;
    END LOOP;

8. What does the next statement in loops do?
a) Skips the current iteration
b) Starts the next loop by ending the current
c) Exits the loop
d) Skips the next line of the loop

9. What is the syntax to use the NEXT statement?
a) NEXT condition loop_label
b) NEXT loop_label WHEN condition
c) loop_label NEXT WHEN condition
d) loop_label NEXT condition

10. It is not possible to write an infinite loop in VHDL.
a) True
b) False

11. The correct syntax for using EXIT in a loop is ___________
a) EXIT loop_label WHEN condition;
b) EXIT WHEN condition loop_label;
c) loop_label WHEN condition EXIT
d) EXIT WHEN loop_label condition

12. FOR loop uses a loop index, the type of loop index is _________
a) STD_LOGIC_VECTOR
b) BIT_VECTOR
c) INTEGER
d) REAL

13. Where do we declare the loop index of a FOR LOOP?
a) Entity
b) Architecture
c) Library
d) It doesn’t have to be declared

14. A FOR loop is inside a WHILE loop. Inside the FOR loop, the EXIT statement is used in such a way that after 4 iterations, it will execute. After the execution of EXIT statement, the control will be passed ________
a) Outside the FOR loop
b) Outside the WHILE loop
c) At the next iteration of WHILE loop
d) At the next iteration of FOR loop

15. A for loop is initiated as given below, in total how many iterations will be there for the FOR loop?

FOR i IN 0 TO 5 LOOP

a) 3
b) 4
c) 5
d) 6

16. All types of FOR loops are synthesizable.
a) True
b) False

17. What is the use of EXIT statement in a loop?
a) For skipping one execution
b) For repeating one statement in the loop
c) For ending the condition and creating infinite loop
d) For ending the loop

18. On what side of the assignment statement, one can use a loop index?
a) Left
b) Right
c) Left or Right
d) Loop index can’t be used in an assignment

19. A WHILE loop is more flexible than FOR loop.
a) True
b) False

20. The FOR loop is not synthesizable if it contains ______ statement.
a) WHEN
b) THEN
c) WAIT
d) IF

21. Which logic circuit is described in the following code?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
 
ENTITY system IS
GENERIC (l : INTEGER := 3);
PORT ( a, b : IN STD_LOGIC_VECTOR ( l DOWNTO 0);
              c     : IN STD_LOGIC;
              x     : OUT STD_LOGIC_VECTOR (l DOWNTO 0)
              y     : OUT STD_LOGIC);
END system;
ARCHITECTURE design OF system IS
BEGIN
PROCESS (a, b, c)
VARIABLE z : STD_LOGIC_VECTOR ( l DOWNTO 0);
BEGIN
z(0) := c;
FOR I IN 0 TO l LOOP
x(i) < = a(i) XOR b(i) XOR z(i);
z(i+1) <= (a(i) AND b(i)) OR (a(i) AND z(i)) OR (b(i) AND z(i));
END LOOP;
y <= z(l);
END PROCESS;
END design;

a) 4-bit full subtractor
b) 4-bit half subtractor
c) 4-bit half adder
d) 4-bit full adder

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