Process Statement – 2 MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Process Statement – 2″.

1. The process can be __________ by using WAIT statements.
a) Suspended
b) Resumed
c) Suspended as well as resumed
d) Cannot be determined

2. A postponed process runs when ___________
a) All the other processes have completed
b) After completion of one particular process
c) Concurrently with all other processes
d) First of all processes

3. It is possible to use sensitivity list and wait statements in the same process.
a) True
b) False

4. Which of the following statement can’t be used inside a process?
a) WAIT
b) IF ELSE
c) Variable declaration
d) PORT MAP

5. The value of y is initially 1 and it is changed after one delta cycle to 0. How many delta cycles (starting from the beginning) will be taken to change the initial value of z, refer to the process given below?

PROCESS (y)
BEGIN
x <=y;
z <= NOT y;
END PROCESS

a) 1
b) 2
c) 3
d) 4

6. Which of the following signal cause the process to execute?

PROCESS (clr)
BEGIN
IF (clr = ‘1’) THEN
y <= ‘0’;
ELSE
y <= input;
END PROCESS;

a) input
b) y
c) clr
d) x

7. A combinational process must have all the _________ signals in its sensitivity list.
a) Input
b) Output
c) Declared
d) Used

8. Which of the following circuit can’t be described without using a process statement?
a) Multiplexer
b) D flip-flop
c) Decoder
d) Comparator

9. There is no restriction on the number of wait statements inside a process.
a) True
b) False

10. Which of the following signal uses keyword EVENT?
a) Variables
b) Output
c) Input
d) Clock

11. Refer to the code given below, what kind of circuit is designed?

SIGNAL x : IN BIT;
SIGNAL y : OUT BIT;
SIGNAL clk : IN BIT;
PROCESS (clk)
BEGIN
IF (clk’EVENT and clk = ‘1’)
y ;&lt= x;
END PROCESS

a) Buffer
b) Latch
c) Flip flop
d) Shift Register

12. The resolution function is needed to resolve the value of _______

PROCESS ()
BEGIN
y <= x;
y <= z;
END PROCESS;

a) z
b) y
c) x
d) No x, y and z

13. The driver(s) of signal y is _________

PROCESS ()
BEGIN
y <= ‘1’;
y <= x;
y <= z;
END PROCESS;

a) z
b) x
c) x and z
d) 1

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