This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “RTL Simulation”.
1. RTL is a design abstraction of what kind of circuit?
a) Asynchronous digital circuit
b) Synchronous digital circuit
c) Asynchronous sequential circuit
d) Analog circuit
3. RTL is used in HDL to create what level of representations in the circuit?
d) Same level
4. What does RTL in digital circuit design stand for?
a) Register transfer language
b) Register transfer logic
c) Register transfer level
d) Resistor-transistor logic
5. RTL mainly focuses on describing the flow of signals between ________
a) Logic gates
6. Which of the following tool performs logic optimization?
a) Simulation tool
b) Synthesis tool
c) Routing tool
d) RTL compiler
7. Setup time is the time required for input data to settle after the triggering edge of the clock.
8. RTL is a combination of both combinational and sequential circuits.
9. Hold time is the time needed for the data to ________ after the edge of the clock is triggered.
c) Remain constant
10. Conversion of RTL description to Boolean _______ description is a function of the translation procedure in the synthesis process.
d) PLA format
11. Simulator enters in which phase after the initialization phase?
a) Execution phase
b) Compilation phase
c) Elaboration phase
d) Simulation phase