RTL Simulation

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “RTL Simulation”.

1. What does RTL in digital circuit design stand for?
a) Register transfer language
b) Register transfer logic
c) Register transfer level
d) Resistor-transistor logic

2. RTL is a design abstraction of what kind of circuit?
a) Asynchronous digital circuit
b) Synchronous digital circuit
c) Asynchronous sequential circuit
d) Analog circuit

3. RTL is used in HDL to create what level of representations in the circuit?
a) High-level
b) Low-level
c) Mid-level
d) Same level

4. RTL mainly focuses on describing the flow of signals between ________
a) Logic gates
b) Registers
c) Clock
d) Inverter

5. Which flip-flop is usually used in the implementation of the registers?
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) J-K flip-flop

6. Which of the following tool performs logic optimization?
a) Simulation tool
b) Synthesis tool
c) Routing tool
d) RTL compiler
.

7. RTL is a combination of both combinational and sequential circuits.
a) True
b) False

8. Setup time is the time required for input data to settle after the triggering edge of the clock.
a) True
b) False

9. Hold time is the time needed for the data to ________ after the edge of the clock is triggered.
a) Decrease
b) Increase
c) Remain constant
d) Negate

10. Simulator enters in which phase after the initialization phase?
a) Execution phase
b) Compilation phase
c) Elaboration phase
d) Simulation phase

11. Conversion of RTL description to Boolean _______ description is a function of the translation procedure in the synthesis process.
a) Optimized
b) Unoptimized
c) Translation
d) PLA format

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