Signal Assignment – 2 MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Signal Assignment – 2″.

1. Those statement which are placed under ________ are concurrent.
a) Process
b) Function
c) Architecture
d) Procedure

2. In case of concurrent assignment, order of statements doesn’t matter.
a) True
b) False

3. The selected concurrent statement is equivalent to ________ sequential statement.
a) If else
b) Loop
c) Wait
d) Case

4. Which of the following can’t be implemented with concurrent statements only?
a) Multiplexer
b) Decoder
c) Adder
d) Counter

5. In the signal assignment statement, which delay is used?

x <= 1 AFTER 10ns

a) Transport delay
b) Inertial delay
c) Delta delay
d) Wire delay

6. Variable assignment statement executes in ______ time.
a) Immediately(zero)
b) After delay specified
c) After one clock cycle
d) After two clock cycles

7. Inertial delay in Signal assignment is useful to ___________
a) Specify wire delay
b) Accumulate delay
c) Ignore input glitches
d) No use

8. Which of the following statement can’t be used to assign values in behavioral modeling of OR Gate?
a) Simple concurrent assignment
b) Sequential assignment
c) Conditional concurrent assignment
d) Selected concurrent assignment

9. Which of the following statement is a zero delay statement?
a) y <= x AFTER 10 ns
b) y <= TRANSPORT x AFTER 10 ns
c) y <= x
d) y := x AFTER 10 ns

10. OTHERS keyword is used with which kind of assignment?
a) Concurrent
b) Sequential
c) Selected
d) Conditional

11. Which of the following is not an assignment statement?
a) <=
b) :=
c) =>
d) :>

12. The following code represents which of the logic gates?

WITH ab SELECT
y <= 1 WHEN “11”;0	WHEN OTHERS;

a) And gate
b) Or gate
c) Not gate
d) Nand gate

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