Signal vs Variables – 1 MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Signal vs Variables – 1″.

1. What is the use of a variable?
a) To represent local value
b) To represent default value
c) To set default value
d) To declare a subprogram

2. Use of constants is to _________
a) Represent wires
b) Represent local information
c) Represent default value
d) Pass value between entities

3. Which of the following is the correct use of the signal?
a) To set a default value
b) To pass value between circuits
c) To declare a variable
d) To represent local information

4. How to declare a constant in VHDL?
a) CONSTANT name : type := value;
b) CONSTANT name := value;
c) CONSTANT name := type := value;
d) CONSTANT name := type : value;

5. A constant is declared in Architecture, it will be accessible in ________
a) Whole code
b) Within the same architecture
c) In the entity associated and corresponding architecture
d) In the process within the architecture

6. Which of the following is local to the block in which it is declared?
a) Signal
b) Integer
c) Constant
d) Variable

7. A user wants a constant to be declared in such a way that it can be accessible by whole code, where should the user declare this constant?
a) Package
b) Entity
c) Architecture
d) Configuration

8. Which of the following can’t be declared in an architecture?
a) Signal
b) Constant
c) Variable

9. Which of the following is the default type of ports of an entity?
a) Variables
b) Constants
c) Signals
d) Functions

10. What is the scope of a constant declared in an entity?
a) Local to the entity
b) Global to the whole code
c) Local to the port
d) Global to the entity and all the architecture associated

Leave a Reply

Your email address will not be published. Required fields are marked *