Signal vs Variables – 2 MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Signal vs Variables – 2″.

1. When a signal is assigned a value inside a process, then the value of a signal is updated _________
a) Immediately
b) After one delta cycle
c) At the end of the corresponding process
d) At the end of architecture

2. A variable is assigned a value inside a process, the new value of the variable will be available _______
a) After one delta cycle
b) Immediately
c) At the end of a process
d) At the end of architectur

3. Which data object can’t be declared inside a process?
a) Signal
b) Variable
c) Constant
d) Integer

4. A variable can be used outside the process i.e. in the architecture.
a) True
b) False

5. When there is no delay specified in a signal assignment (concurrent), the delay will be _______
a) Zero
b) Transport delay
c) Inertial delay
d) Delta delay

6. Which of the following needs no evaluation of drivers?
a) Signals
b) Variables
c) Process
d) Functions

7. There are no delays in case of variables.
a) True
b) False

8. During synthesis, a variable infers ________
a) Flip flop
b) Register
c) Wire
d) Variables are not synthesizable

9. In which of the following, the right hand side of an assignment is a waveform element?
a) Signal
b) Variable
c) Constant
d) Process

10. What is there in right hand side of a variable assignment?
a) Time expressions
b) Waveform elements
c) Delays
d) Simple expressions

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