Signal vs Variables

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Signal vs Variables”.

1. Which of the following is the correct use of the signal?
a) To set a default value
b) To pass value between circuits
c) To declare a variable
d) To represent local information

2. What is the use of a variable?
a) To represent local value
b) To represent default value
c) To set default value
d) To declare a subprogram

3. Use of constants is to _________
a) Represent wires
b) Represent local information
c) Represent default value
d) Pass value between entities

4. How to declare a constant in VHDL?
a) CONSTANT name : type := value;
b) CONSTANT name := value;
c) CONSTANT name := type := value;
d) CONSTANT name := type : value;

5. Which of the following is local to the block in which it is declared?
a) Signal
b) Integer
c) Constant
d) Variable

6. A constant is declared in Architecture, it will be accessible in ________
a) Whole code
b) Within the same architecture
c) In the entity associated and corresponding architecture
d) In the process within the architecture

7. Which of the following can’t be declared in an architecture?
a) Signal
b) Constant
c) Variable
d) BIT_VECTOR

8. What is the scope of a constant declared in an entity?
a) Local to the entity
b) Global to the whole code
c) Local to the port
d) Global to the entity and all the architecture associated

9. A user wants a constant to be declared in such a way that it can be accessible by whole code, where should the user declare this constant?
a) Package
b) Entity
c) Architecture
d) Configuration

10. Which of the following is the default type of ports of an entity?
a) Variables
b) Constants
c) Signals
d) Functions

11. Which data object can’t be declared inside a process?
a) Signal
b) Variable
c) Constant
d) Integer

12. When a signal is assigned a value inside a process, then the value of a signal is updated _________
a) Immediately
b) After one delta cycle
c) At the end of the corresponding process
d) At the end of architecture

13. A variable is assigned a value inside a process, the new value of the variable will be available _______
a) After one delta cycle
b) Immediately
c) At the end of a process
d) At the end of architecture

14. A variable can be used outside the process i.e. in the architecture.
a) True
b) False

15. There are no delays in case of variables.
a) True
b) False

16. When there is no delay specified in a signal assignment (concurrent), the delay will be _______
a) Zero
b) Transport delay
c) Inertial delay
d) Delta delay

17. During synthesis, a variable infers ________
a) Flip flop
b) Register
c) Wire
d) Variables are not synthesizable

18. In which of the following, the right hand side of an assignment is a waveform element?
a) Signal
b) Variable
c) Constant
d) Process

19. Which of the following needs no evaluation of drivers?
a) Signals
b) Variables
c) Process
d) Functions

20. What is there in right hand side of a variable assignment?
a) Time expressions
b) Waveform elements
c) Delays
d) Simple expressions

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