Structural Modelling – 1 MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Structural Modelling – 1″.

1. Which of the following is not a way of partitioning a design?
a) Component
b) Block statement
c) Processes
d) Generics

2. What is the basic unit of structural modeling?
a) Process
b) Component declaration
c) Component instantiation
d) Block

3. Which of the following is similar to the entity declaration in structural modeling?
a) Component instantiation
b) Component declaration
c) Port map
d) Generic map

4. Which of the following is defined in structural modeling?
a) The structure of circuit
b) Behavior of circuit on different inputs
c) Data flow from input to output
d) Functional structure

5. What do you mean by component instantiation?
a) To use the component
b) To describe external interface of the component
c) To declare the gate level components
d) To remove any component from the design

6. Which of the following is correct syntax for component declaration?
a)

     COMPONENT component_name IS
     PORT ( port_mode : type port_name;
     port_mode : type port_name;
     ….);
     END component_name;

b)

     COMPONENT component_name IS
     PORT ( port_mode : type port_name;
     port_mode : type port_name;
     ….);
     END COMPONENT;

c)

     COMPONENT component_name IS
     PORT ( port_name : mode type;
     port_name : mode type;
      ….);
      END component_name;

d)

     COMPONENT component_name IS
     PORT ( port_name : mode type;
     port_name : mode type;
      ….);
      END COMPONENT;

7. The structural model is similar to___________
a) Boolean relations of the circuit
b) Schematic block diagram of the circuit
c) Timing relations of the circuit
d) Components of the circuit

8. Which of the following is the correct syntax for component instantiation?
a) instantiate : component_name PORT MAP (port_list);
b) label : instantiate COMPONENT PORT MAP (port_list);
c) label : component_name PORT MAP (port_list);
d) label : instantiate component_name PORT MAP (port_list)

9. Which of the following must be known to describe a structural model in VHDL?
a) Number of inputs and outputs
b) Components and their connections
c) Relation between inputs and outputs
d) Value of output for different input combinations

10. It is possible to use a component twice which was declared only once.
a) True
b) False

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