Structural Modelling

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Structural Modelling – 1”.

1. Which of the following is defined in structural modeling?
a) The structure of circuit
b) Behavior of circuit on different inputs
c) Data flow from input to output
d) Functional structure

2. Which of the following is not a way of partitioning a design?
a) Component
b) Block statement
c) Processes
d) Generics

3. What is the basic unit of structural modeling?
a) Process
b) Component declaration
c) Component instantiation
d) Block

4. Which of the following is similar to the entity declaration in structural modeling?
a) Component instantiation
b) Component declaration
c) Port map
d) Generic map

5. What do you mean by component instantiation?
a) To use the component
b) To describe external interface of the component
c) To declare the gate level components
d) To remove any component from the design

6. The structural model is similar to___________
a) Boolean relations of the circuit
b) Schematic block diagram of the circuit
c) Timing relations of the circuit
d) Components of the circuit
.

7. Which of the following is correct syntax for component declaration?
a)

     COMPONENT component_name IS
     PORT ( port_mode : type port_name;
     port_mode : type port_name;
     ….);
     END component_name;

b)

     COMPONENT component_name IS
     PORT ( port_mode : type port_name;
     port_mode : type port_name;
     ….);
     END COMPONENT;

c)

     COMPONENT component_name IS
     PORT ( port_name : mode type;
     port_name : mode type;
      ….);
      END component_name;

d)

     COMPONENT component_name IS
     PORT ( port_name : mode type;
     port_name : mode type;
      ….);
      END COMPONENT;

 

8. Which of the following is the correct syntax for component instantiation?
a) instantiate : component_name PORT MAP (port_list);
b) label : instantiate COMPONENT PORT MAP (port_list);
c) label : component_name PORT MAP (port_list);
d) label : instantiate component_name PORT MAP (port_list)

9. It is possible to use a component twice which was declared only once.
a) True
b) False

10. Which of the following must be known to describe a structural model in VHDL?
a) Number of inputs and outputs
b) Components and their connections
c) Relation between inputs and outputs
d) Value of output for different input combinations

11. In which part of the VHDL code, components must be declared?
a) Library
b) Entity
c) Architecture
d) Configuration

12. Which of the following function is used to map the component?
a) COMPONENT INSTANTIATE
b) PORT MAP
c) GENERIC MAP
d) USE

13. How many ways are there in VHDL to map the components?
a) 1
b) 2
c) 3
d) 4

14. What is the property of Positional mapping?
a) Easier to write
b) Less error prone
c) Ports can be left unconnected
d) Difficult to write

15. __________ mapping is less error prone.
a) Port
b) Positional
c) Nominal
d) Generic

16. A component has 3 ports- two inputs(a and b) and one output(y). Which of the following statement is for the positional mapping of the component?
a) LABEL : my_component PORT MAP (l, m, n);
b) LABEL : my_component PORT MAP (y, a);
c) LABEL : my_component PORT MAP (l => a, m => b, n => y);
d) LABEL : my_component PORT MAP(a, b, y>= a);

17. The ports of a component can be left unconnected.
a) True
b) False

18. Which of the following is the right way to leave a port unconnected?
a) L1 : my_component PORT MAP(a); a <= OPEN;
b) L1 : my_component PORT MAP(a := OPEN);
c) L1: my_component PORT MAP(a => OPEN);
d) L1 : my_component PORT MAP(a); a := OPEN;

19. It is not necessary that the order of the arguments in PORT MAP is taken as the order in which ports are declared.
a) True
b) False

20. How to declare a 2 input OR gate in the structural modeling?
a)

    COMPONENT or IS
     PORT ( a, b : IN BIT;
                  x, y : OUT BIT);
    END COMPONENT;

b)

     COMPONENT or IS
     PORT ( a, b : IN BIT;
                  y : OUT BIT);
    END COMPONENT;

c)

    COMPONENT or_gate IS
     PORT ( a, b : IN BIT;
                  x,  y : OUT BIT);
    END COMPONENT;

d)

    COMPONENT or_gate IS
     PORT ( a, b : IN BIT;
                  y : OUT BIT);
    END COMPONENT;

21. Which of the following is the correct order for a structural model in VHDL?
a) Libraries, Entity declaration, Component declaration, Component instantiation
b) Libraries, Component declaration, Entity declaration, Component instantiation
c) Libraries, Entity declaration, Component instantiation, Component declaration
d) Component declaration, Libraries, Entity declaration, Component instantiation

22. Refer to the model given below, which circuit is designed?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, x);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, y);
END arch1;

a) Half adder
b) Comparator 2- bits
c) Full adder
d) Can’t be determined

23. There is a special function called interconnect () to define interconnections between pins.
a) True
b) False

24. Refer to the architecture given below, there are two outputs called x and y. The structure defined is a full adder circuit. Which of the outputs corresponds to sum output of the adder?

ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, y);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, x);
END arch1;

a) y
b) x
c) s5
d) c

25. Which modeling style is used in code given below?

ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
Architecture arch OF design IS
BEGIN
x &lt;= a XOR b XOR c;
y &lt;= (a AND b) OR (b AND c) OR (a AND c);
END arch;
ARCHITECTURE arch1 OF design IS
COMPONENT comp1 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp3 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: comp1 PORT MAP(a, b, s1);
X2 : comp1 PORT MAP(s1, c, x);
X3: comp2 PORT MAP(a, b, s2);
X4 : comp2 PORT MAP(a, c, s3);
X5: comp2 PORT MAP(b, c, s4);
X6: comp3 PORT MAP(s2, s3, s5);
X7: comp3 PORT MAP(s4, s5, y);
END arch1;

a) Behavioral and structural
b) Structural
c) Dataflow
d) Dataflow and Structural

26. What is the correct syntax for mapping a GENERIC parameter in structural modeling?
a) label : component_name GENERIC MAP(parameter_list) PORT MAP(port_list)
b) label : component_name GENERIC MAP(parameter_list)
c) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)
d) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)

27. It is possible to use a GENERIC parameter as a separate component.
a) True
b) False

.

28. A component instantiation statement generates a(n) _______ of the component.
a) Class
b) Behavior
c) Structure
d) Object

29. The structural code for 4-bit adder is given below.

COMPONENT adder IS
GENERIC (n : INTEGER := 3);
PORT(input : IN BIT_VECTOR(n DOWNTO 0);
output : OUT BIT_VECTOR(n DOWNTO 0));
END COMPONENT;

If user want to convert this in an 8 bit adder, which of the following variable should be changed?
a) n
b) input
c) output
d) component

30. What is the other name for implicit mapping?
a) Nominal mapping
b) Positional mapping
c) Explicit mapping
d) Inclusive mapping

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