Synchronous and Asynchronous Reset

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Synchronous and Asynchronous Reset”.

1. Reset is a signal that is used for the initialization of the hardware.
a) True
b) False

2. How many types of resets are there in hardware design?
a) One
b) Two
c) Three
d) Four

3. In synchronous reset, reset is sampled with respect to _______
a) Enable signal
b) Data input signal
c) Clock signal
d) Output signal

4. Which of the following is an advantage of a synchronous reset?
a) It is slow
b) It requires a clock signal to reset the circuit
c) It filters the reset signal
d) It needs a stretched reset

5. In asynchronous reset, reset is sampled independently of the _______
a) Enable signal
b) Data input signal
c) Clock signal
d) Output signal
View AnswerAnswer: c
Explanation: In asynchronous reset, reset is sampled independently of the clock signal. It means, after the reset signal is enabled, it will start effective immediately and it will not wait or check for the clock edges.

6. Synchronous reset is a fast reset.
a) True
b) False
.

7. Which of the following is NOT an advantage of asynchronous reset?
a) It is fast
b) It doesn’t require a clock signal to reset the circuit
c) Reset gets the highest priority
d) It may cause metastability

8. Asynchronous circuit is also called ________ circuit.
a) Combinational
b) Self-timed
c) Clock circuit
d) Delayed

9. Designation used by a flip-flop for the reset is ________
a) PRE
b) CLR
c) D
d) Q

10. Preset and clear are asynchronous inputs.
a) True
b) False

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