Top Level System Design

VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Top Level System Design”.

1. The top-level system design is modelled for functionality and performance.
a) True
b) False

2. Which modelling is used in the top-level system design?
a) Low-level behavioural modelling
b) High-level behavioural modelling
c) Structural modelling
d) Data flow modelling

3. What are the two constructs used in most of the behavioural modelling?
a) Assign
b) Begin and end
c) Initial and always
d) Always and end

4. How many levels of abstraction are there in the top-level system design?
a) One
b) Two
c) Three
d) Four

5. Timing performance of design is checked by which of the following simulation mode?
a) Gate-level
b) Behavioural
c) Transistor-level
d) Switch-level

6. The statements in the initial construct constitute ________
a) End block
b) Initial block
c) Begin block
d) Always block

7. The statements in the always construct constitute ________
a) End block
b) Initial block
c) Begin block
d) Always block

8. Register data types and memory data types are updated by procedural assignments.
a) True
b) False

9. How many types of procedural assignments are there?
a) One
b) Two
c) Three
d) Four

10. In which order do the blocking assignment statements are executed in a sequential block?
a) Random order
b) Specified order
c) Ascending order
d) Descending order

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