# Triggering of Flip Flops MCQ’s

This set of Digital Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Triggering of Flip Flops”.

1. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop

2. In J-K flip-flop, the function K=J is used to realize _____________
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop

3. The characteristic equation of J-K flip-flop is ______________
a) Q(n+1)=JQ(n)+K’Q(n)
b) Q(n+1)=J’Q(n)+KQ'(n)
c) Q(n+1)=JQ'(n)+KQ(n)
d) Q(n+1)=JQ'(n)+K’Q(n)

4. The only difference between a combinational circuit and a flip-flop is that _____________
a) The flip-flop requires previous state
b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) The flip-flop depends on the past as well as present states

5. The flip-flop is only activated by _____________
a) Positive edge trigger
b) Negative edge trigger
c) Either positive or Negative edge trigger
d) Sinusoidal trigger

6. Both the J-K & the T flip-flop are derived from the basic _____________
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop

7. How many stable states combinational circuits have?
a) 3
b) 4
c) 2
d) 5

8. The S-R latch composed of NAND gates is called an active low circuit because _____________
a) It is only activated by a positive level trigger
b) It is only activated by a negative level trigger
c) It is only activated by either a positive or negative level trigger
d) It is only activated by sinusoidal trigger

9. The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T

10. What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered

11. What does the half circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered

12. What does the triangle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Edge triggered
c) Both Level enabled & Edge triggered
d) Level triggered

13. What does the direct line on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered

14. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is _____________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave

15. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW