# Up Down Counter MCQ’s

This set of Digital Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Up Down Counter”.

1. UP-DOWN counter is also known as ___________
a) Dual counter
b) Multi counter
c) Multimode counter
d) Two Counter

2. In an UP-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop

3. UP-DOWN counter is a combination of ____________
a) Latches
b) Flip-flops
c) UP counter
d) Up counter & down counter

4. In DOWN-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop

5. Once an up-/down-counter begins its count sequence, it ___________
a) Starts counting
b) Can be reversed
c) Can’t be reversed
d) Can be altered

6. A modulus-10 counter must have ________
a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
d) Synchronous clocking

7. Binary counter that count incrementally and decrement is called ___________
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter

8. In 4-bit up-down counter, how many flip-flops are required?
a) 2
b) 3
c) 4
d) 5

9. Which is not an example of a truncated modulus?
a) 8
b) 9
c) 11
d) 15

10. An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________
a) Taking the output on the other side of the flip-flops (instead of Q)
b) Clocking of each succeeding flip-flop from the other side (instead of Q)
c) Changing the flip-flops to trailing edge triggering
d) All of the Mentioned

11. The designation means that the ________
a) Up count is active-HIGH, the down count is active-LOW
b) Up count is active-LOW, the down count is active-HIGH
c) Up and down counts are both active-LOW
d) Up and down counts are both active-HIGH

12. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz