WAIT Statements – 1 MCQ’s

Electronics & Communication Engineering VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “WAIT Statements – 1″.

1. Which of the following can’t be used in a process when it has any WAIT statement?
a) IF
b) CASE
c) LOOP
d) Sensitivity list

2. How many forms of WAIT statement are there in VHDL?
a) 1
b) 2
c) 3
d) 4

3. WAIT statement can’t appear under _______ directly.
a) Architecture
b) Process
c) Procedure
d) Subprogram

4. Which of the following is not the correct WAIT statement?
a) WAIT ON
b) WAIT WHILE
c) WAIT FOR
d) WAIT UNTIL

5. What is the correct syntax for using a WAIT UNTIL statement?
a) WAIT UNTIL boolean_condition_or_expression;
b) WAIT UNTIL signal_name;
c) WAIT UNTIL time_value_or_expression;
d) WAIT UNTIL boolean_expression time_value;

6. WAIT UNTIL statements cause the process to wait ________
a) When a signal changes value
b) Until a condition is true
c) For a specific time period
d) When either a signal changes its value or a condition comes true

7. What is the use of WAIT FOR statement?
a) To stop execution when the condition is false
b) To stop execution until a signal changes its value
c) To stop execution for a specific time period
d) To stop execution until the clock event occurs

8. Which of the following is the correct use of WAIT ON statement?
a) To stop execution until a signal changes its value
b) To stop execution when a signal changes its value
c) To stop execution when a condition specified is true
d) To stop execution when a condition specified is false

9. How to define a WAIT FOR statement?
a) WAIT FOR signal_name;
b) WAIT FOR booelan_expression;
c) WAIT FOR clock_event;
d) WAIT FOR time_value;

10. Which of the following is correct syntax for WAIT ON statement?
a) WAIT ON signal_assignments;
b) WAIT ON boolean_condition;
c) WAIT ON signal_list;
d) WAIT ON time_expression;

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