WAIT Statements – 3 MCQ’s

Electronics & Communication Engineering VHDL

This set of Digital Signal Processing Multiple Choice Questions & Answers (MCQs) focuses on “WAIT Statements – 3”.

1. Which of the following is true about WAIT ON statement?
a) WAIT ON statement is supported by synthesis tools
b) WAIT ON statement is not supported by synthesis tools
c) WAIT ON statement is supported in a clocked process only
d) WAIT ON statement is supported in a combinational process

2. In a procedure, __________ statement is not supported.
a) WAIT UNTIL
b) WAIT ON
c) WAIT FOR
d) WAIT FOR and unconditional WAIT

3. Which of the following is true about WAIT UNTIL statement?
a) WAIT UNTIL statement is supported by synthesis tools
b) WAIT UNTIL statement is not supported by synthesis tools
c) WAIT UNTIL statement is supported in a clocked process only
d) WAIT UNTIL statement is supported in a combinational process

4. What kind of circuit is implemented by the following architecture?

ARCHITECTURE my_arch OF my_design IS
BEGIN
PROCESS
BEGIN
WAIT ON clk;
IF(clk = ‘1’) THEN
y <= x;
END IF;
END PROCESS;
END my_arch;

a) D flip flop
b) Inverter
c) OR gate
d) Shift register

5. A user wants to assign a signal after a wait of 20 ns. The process used has a sensitivity list. What is the possible way to achieve this?
a) By using WAIT FOR statement
b) By using AFTER clause
c) By using a separate process
d) By using WAIT ON statement

6. WAIT FOR statement is useful only for _________
a) Synthesis
b) Simulation
c) Gate level implementation
d) Optimization

7. Since WAIT statement can’t be synthesized many times, how a clock event can be detected then?
a) By using IF(clk = ‘1’)
b) By using ‘EVENT keyword
c) By using a CASE statement
d) By using a LOOP

8. Which of the following can be used to make the process wait indefinitely?
a) WAIT FOR indefinite ns;
b) WAIT UNTIL false;
c) WAIT;
d) WAIT UNTIL true;

9. A wait statement can have label preceding it.
a) True
b) False

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